1. Field of the Invention
The present invention relates to an interface between a first voltage domain and a second voltage domain. More particularly, this invention relates to such interfaces which are configured to retain data.
2. Description of the Prior Art
Contemporary system-on-chip (SoC) devices are commonly designed to consume as little power as possible. This has clear advantages, for example when the SoC is implemented in mobile or hand-held devices the battery life is prolonged. One aspect of such design is that the SoC is typically arranged to be powered by as low a voltage supply as can be tolerated, whilst still ensuring correct functionality of the SoC components. Contemporary SoC voltage supplies are commonly below 1V (e.g. VDD=0.7V).
Although the SoC itself may operate in such a low voltage domain, it is often the case that the SoC must communicate with other off-chip components which operate in a higher voltage domain (e.g. DVDD=2V). For this reason it is known to provide an interface between the low and high voltage domains (i.e. on the edge of the chip) to transform low voltage on-chip signals from the SoC into higher voltage signals suitable for the off-chip high voltage domain (and vice versa). This interface is typically provided by a set of I/O drivers arranged around the periphery of the SoC (an “I/O ring”) under the control of an I/O controller, which itself forms part of the SoC. Each I/O driver may be connected to a pad on the edge of the SoC which forms the physical connection to off-chip devices.
A further aspect of the low power design of contemporary SoC devices is that it is commonly arranged that at least part of the SoC can be powered down when not in use to reduce power consumption. This power down may be partial, only selectively powering down components of the SoC that are not in use and are not required to be active, or it may be complete, with the entire SoC being switched off.
Nevertheless, a requirement of some such SoC systems is that data at the interface between the on-chip low voltage domain and the off chip high voltage domain is retained, even when the on-chip components providing the low voltage signals are powered down. For example a display driver may need to continuously drive the same signal, to maintain a particular part of a display in a given state, despite the on-chip component originally driving that signal having been switched off. One manner of implementing this feature is to arrange the I/O ring to enter a retention state, in which the signals that the I/O drivers output to their respective pads are maintained at the values they had before the I/O ring entered the retention state, regardless of subsequent changes in the input signals they receive. In particular, the output signals are maintained, even when the components of the SoC supplying the input signals are powered down.
This functionality is typically achieved by the I/O controller supplying a signal to the I/O ring to drive it into its retention state. Subsequently, when the I/O ring is required to return to its normal transmission state, this is also signalled by the I/O controller. Consequently the I/O controller is required to be a “live core” component, which cannot be powered down with other parts of the SoC, such that the correct control of the I/O ring is provided.
It would be desirable to provide an improved technique for retaining such interface data.